Fwd: Verification Engineer – SystemVerilog/UVM with RISC-V SoC _ Chicago, IL

We have the requirements below with our client. Kindly go through the JD below and let me know your interest.

Role: Verification Engineer – SystemVerilog/UVM with RISC-V SoC

Location: Chicago, IL

Duration: 5 months

Role Description & Key Responsibilities:

#Verification Engineer
• Must have very good System Verilog/UVM experience in developing test benches
• Must have experience with developing test benches with RISC-V based SoC
• RISC-V processor verification is an added advantage
• Should have expertise developing scoreboards, monitors, and checkers
• Should have expertise in functional and code coverage
• Have experience in IP/SoC Verification
• Expertise in AMBA/AXI bus protocols
• Must have USB3.0 verification expertise
• Scripting Language (PERL/Python/Shell/Makefile)
• Must have good debugging and problem-solving skills
• Good to have GLS verification experience
• Educational Qualification: BE/ME or BTech/MTech (BS/MS)

“Tekgence is an equal opportunity employer. Applicants must be authorized to work in the U.S. U.S. citizens and Green Card holders are strongly encouraged to apply.”

Thanks & Best Regards

Bhargavi Jaltar| Talent Acquisition Lead| Tekgence Inc.

Office : bhargavi@tekgence.com